clock signal frequency

基本解释

Direct Digital Synthesize (DDS) is used to generate clock signal at any frequency so that data generator can output data at any rate.
着重分析采用直接数字合成（DDS）技术产生任意频率时钟信号的方法，实现数据发生器以任意码率输出数据；
A first circuit is coupled with the first end of the quartz oscillator and is used for generating a first clock signal with a fixed frequency according to the first signal.
一第一电路耦接于上述石英振荡器的上述第一端，用以根据上述第一信号产生具有固定频率的一第一时钟信号。
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A second circuit is coupled with the second end of the quartz oscillator and is used for generating a second clock signal with a variable frequency according to the second signal.
一第二电路耦接于上述石英振荡器的上述第二端，用以根据上述第二信号产生具有可变频率的一第二时钟信号。
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